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Archive for November, 2010

Specifications for a super-low-cost access and educational device

November 29, 2010 Leave a comment
Wanting to contribute to higher education for everyone? Below is minimum specifications for an access device with this purpose, according to The Near Computer Science & Engineering Department at Indian Institute of Technology Rajasthan (http://www.iitk.ac.in/iitj/Expression%20of%20Interest%20for%20Low%20Cost%20Device.pdf):
Projected base prize assuming 1-10 million devices, including all software and hardware licenses (see link above): $35
  • Mobile system on chip or module meeting quite moderate performance specs (see link above)
  • Qwerty keyboard, mouse, webcam
  • 7” color screen or projector (support for RGB projector required)
  • 2 USB, SD, RGB, ethernet, external HD
  • RF certification according to FCC guidelines (of course!)
  • Three hours usage per charging, charger
  • Shock resistant casing or suitable form factor
  • Normal operation at 0-48 degC temperature, 80% relative humidity, 2g acceleration
  • ROHS Compliant
Prize margin opportunities:
  • WLAN
  • RAM and hard-disk/NAND-flash options
  • Environmental shield
  • Larger screen/projector
  • Touch screen
  • Solar cell or hybrid capacitor replacement for battery
  • HDMI port
  • Playback: AVCHD
  • Multimedia I/O Interfaces: DTV, IPTv, DTH
  • Internet browsing: flash player (adobe)

If interested in streamlining your product suite towards such extreme low-cost and high usability requirements, please contact Quflow for a free (draft) customized feasibility analysis, technical coordination offer and project sponsoring strategy under strictest NDA.

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Categories: Discussions

IC efficiency and speed when quantization matters

November 26, 2010 Leave a comment

Un-intentional effects of electron wave and charge quantization are causing big problems in current integrated circuit (IC) manufacturing as feature sizes get below 50 nm towards the sub-10nm range. It is now high time to make use of the quantization effects instead of fighting them. The basic CMOS transistors used inside most ICs today are getting more and more efficient but also more weak and process-sensitive as their size is reduced. However when the transistor size and bias voltage is so small that barely a single electronic wave mode can propagate (quantum point contacts) Koswatta et al. (http://arxiv.org/ftp/arxiv/papers/1011/1011.5241.pdf) recently showed such tunneling behavior can enhance both the energy efficiency and transistor strength (and therefore also process stability and transistor speed) compared to classical transistor models. Good news for both quantum engineers, IC manufacturers and device users!

Fig. 4. Simulated energy-position resolved current spectrum (log scale) of the 1D BG-TFET (EG-eff = -100meV) with dissipative transport (CNT phonon modes) at VDS = 0.4V and; (a) VGS = 0.4V (above-threshold), and (b) VGS = -0.05V (subthreshold). Phonon absorption-assisted tunneling dominates the TFET off-state leakage. Carrier thermalization in the drain by phonon emission is also observed.

Categories: Research

Researching Moore’s law, …

November 26, 2010 Leave a comment

Researching Moore’s law, nanolithography trends and issues. CMOS replaced by quantum & catalytically grown devices – when and how?

Categories: Uncategorized

Design optimization of coupled systems

November 22, 2010 1 comment

Quflow has experience from training and optimization of neural networks for human factor modeling, with surprisingly good results (http://quflow.com/publications). Recently, Fang et al. (http://tr.ietejournals.org/text.asp?2010/27/4/336/64601) listed how similar Quantum Particle Swarm Optimization (QPSO) methods has been used to successfully optimize global system performance in many engineering disciplines.

Nowadays, optimization is often integrated and relatively easy to use in most design tools. Designers can therefore focus more on analyzing which parameters matter most and let the tool do its job finding a global optimum configuration. This works well within each specific design discipline, however a complete product requires optimization across multiple disciplines simultaneously, and few tools, engineers and application examples exist for this. It would be interesting to see how such products would look like – probably much more organic and chaotic than we are used to, as in the 100% computer-generated WiFi antenna pattern below (from the last reference below) which works very well but raises questions on how it actually works. Optimization is fun, creative and easily leads to completely new ideas and understandings – very much Quflow.

Fragmented WiFi antenna

Categories: Examples, Research

Electron boxing – rules of the game

November 18, 2010 Leave a comment

Shin et al. (http://arxiv.org/ftp/arxiv/papers/1001/1001.3724.pdf) has obtained a very interesting switching diagram for a nearly isolated CMOS transistor close to pinch-out:

Figure 2c: Stability plot at room temperature; each diamond corresponds to a stable charge configuration state with fixed electron occupancy N.

The combined effects from multiple quantizations are causing big problems with current device technologies due to chaotic behavior (unintentional quantum dots and quantum point contacts) within the traditional CMOS circuitry. But as we go even further down in size, the quantization will ultimately lead to enhanced stability and device efficiency – if used correctly as in the single-electron transistor Shen et al measured here.

Categories: Research

Dividing risks = multiplying opportunities

November 8, 2010 1 comment

Baldwin & Woodard (http://www.hbs.edu/research/pdf/09-034.pdf) argue that the fundamental architecture behind all platforms is the partitioning into a set of “core” components with low variety and a complementary set of “peripheral” components with high variety. This achieves economies of scale while reducing the cost of creating a wide variety of complementary components.

Quflow has experience from products that are developed as monolithic designs as well as products that are designed as more generic platforms. The differences are very big. Monolithic designs may appear mature in the beginning but has a jittery quality progress and are difficult to finish, while the partitioned designs always reach and exceed expectations at a fast and steady pace.
Example: The monolithic part to the left in the illustration below did not reach desired quality and project cost targets due to a very jittery quality progress. To the right is the same subsystem in a later product where the risks were considered higher and design responsibilities were more divided.

Monolithic compared to partitioned system

As could have been expected, the quality in the latter product grew very quickly due to proper hardware partitioning and exceeded all expectations at a fraction of the project cost compared to the monolithic design. In fact it was so agile that one of the sub-teams actually took the opportunity to configure in a chipset from the next product generation, contributing to the success of later products as well!

Product quality growth

Usually the argument for not partitioning a product by its design risks is that the partitioning itself introduces risk, cost and size, but nowadays when interfacing components can be very small, cheap and generic, it seldom matters even if partitioning is kept also in the final product. Such products are also very easy to use as platform for further developments and new opportunities. All really successful products create their own unique ecosphere for further developments, and Quflow does systems engineering that makes it very easy to achieve.

Categories: Examples, Research